Jianhui Jiang

PhD, Professor, Doctoral Supervisor @ Software Engineering Theory & Platform

Tel:+86-21-69589713
Email:jhjiang@tongji.edu.cn

Brief Intro:
Jiang Jianhui received his BE degree in railway signaling and ME degree in railway transport automation and communication from Shanghai Institute of Railway Technology, Shanghai, China, in 1985 and 1988, respectively, and the Ph D degree in traffic information engineering and control from Shanghai Tiedao University, Shanghai, China, in 1999.
He is currently a full professor of software engineering and Vice Dean of School of Software Engineering at Tongji University. He was a Chair of Department of Computer Science and Technology, College of Electronics and Information Engineering, Tongji University from 2007 to 2011. He had serviced as a member of the Editorial Board of the Journal of Circuits and Systems sponsored by Guangzhou Institute of Electronic Technology, Chinese Academy of Sciences. He is a Vice Director of Technical Committee on Fault-tolerant Computing, a member of Technical Committee on Microcomputer, Chinese Computer Federation (CCF), and a member of several technical committees of Shanghai Computer Society. He has served on several program committees of national or international symposiums or workshops including IEEE Pacific Rim International Symposium on Dependable Computing, IEEE Asian Test Symposium, IEEE Workshop on RTL and High-Level Testing. He has coauthored two books and published more than 150 technical papers.

 

Teaching:
Software Reliability Engineering, Dependable Systems, Secure Architecture and Management

 

Research:
Dependable Systems and Networks, Software Reliability Engineering, VLSI/SoC Test and Fault Tolerance, Real-time Systems, Reconfigurable Systems

 

Selected Publications:
Dependable Systems and Networks
[1] Yun Chunxin, Jiang Jianhui, Safety critical computer systems, China Railway Publishing House, Beijing, 2003 (in Chinese)
[2] Jiang Jianhui, "Fail-safe technology and self-checking technology", in Computer Fault-Tolerant Technology, Chapter 5, Hu Mou (editor), China Railway Publishing House, Beijing, 1995, pp. 157-199 (in Chinese)
[3] Shuai Chunyan, Jiang Jianhui, Ouyang Xin, Chen Linbo, Yang Yang, "An alert hierarchical association algorithm to construct attack scenarios," Information - An International Interdisciplinary Journal, Vol. 15, No. 1, pp. 113-121, 2012
[4] Chunyan Shuai, Jianhui Jiang, Xin Ouyang, "A lightweight cooperative detection framework of DDoS/DoS attacks based on counting bloom filter," Journal of Theoretical and Applied Information Technology, Vol. 45, No. 1, pp. 160-167, 2012
[5] CHEN Linbo, JIANG Jianhui, ZHANG Danqing, "Stack buffer overflow prevention based on dual-stack," Journal of Tongji University (Nature Science), Vol. 40, No. 3, pp. 452-458, 2012 (in Chinese)
[6] ZHOU Huansheng, JIANG Jianhui, "A multidimensional security index system and quantitative level protection model," Journal of University of Science and Technology of China, Vol. 42, No. 1, pp. 67-76, 2012 (in Chinese)
[7] Jie YIN, Jianhui JIANG, Yu LIU, "AC-RMT: A fault-tolerance SMT architecture based on asynchronous checkpoint," Intelligent Automation and Soft Computing, Vol. 17, No. 6, pp. 803-813, 2011
[8] Jie Yin and Jianhui Jiang, "Easing instruction queue competition among threads in RMT," Journal of Computers, Vol. 6, No. 7, pp. 1394-1401, 2011
[9] Yin Jie and Jiang Jianhui, "The matching share allocation strategy of rename registers for redundant multithreading architectures," Journal of Computer Research and Development, Vol. 48, No. 3, pp. 516-527, 2011 (in Chinese)
[10] CHEN Linbo, JIANG Jianhui, ZHANG Danqing, Shuai Chunyan, "An intrusion tolerant system based on multi-version redundant processes," Journal of Tsinghua University (Science and Technology), Vol. 51, No. S1, pp. 1519-1526, 2011 (in Chinese)
[11] Yang Yang, Shuai Chunyan, and Jiang Jianhui, "A buffer overflow detection approach on stack analysis," Journal of Computer Research and Development, Vol. 47, No. S, pp. 291-295, 2011 (in Chinese)
[12] Jiang Jian-hui, Zhang Li-yuan, Jin Tao, Chen Chuan, "Dynamic buffer overflow prevention based on k circular random sequence," Journal of Tongji University (Nature Science), Vol. 38, No. 6, pp. 917-924, 2010 (in Chinese)
[13] TIAN Chun-Qi, JIANG Jian-Hui, HU Zhi-Guo, LI Feng, "A novel super-peer based trust model for peer-to-peer networks," Chinese Journal of Computers, Vol. 33, No. 2, pp. 345-355, 2010 (in Chinese)
[14] WANG Zhen, JIANG Jian-Hui, YUN Chun-Xin, "Error-correcting techniques for high-performance processors," Journal of Computer Research and Development, Vol. 45, No. 2, pp. 358-366, 2008 (in Chinese)
[15] JIANG Jianhui, MIN Yinghua, and PENG Chenglian, "Fault-tolerant systems with concurrent error-locating capability," Journal of Computer Science and Technology, Vol. 18, No. 2, pp. 190-200, 2003
[16] JIANG Jian-Hui, MIN Ying-Hua, and PENG Cheng-Lian, "Concurrent error locatable N-modular redundancy structure with even N," Chinese Journal of Computers, Vol. 25, No. 8, pp. 837-844, 2002 (in Chinese)
[17] JIANG Jian-Hui, "Alternating-complementary locator and its use for error location in dual-modular redundancy with comparison structure," Journal of Computer Research and Development, Vol. 38, No. 6, pp. 754-764, 2001 (in Chinese)
[18] Jianhui Jiang and Hongbao Shi. Robust fail-safe systems with fault location capability. ACTA ELECTRONICA SINICA, 2000, 28(8): 35-38 (in Chinese)
[19] Chen Linbo, Jiang Jianhui and Zhang Danqing, "Prevent code reuse attacks by using control flow lazily check," Proceedings of IEEE 18th Pacific Rim International Symposium on Dependable Computing, Niigata, Japan, Dec 2012, pp. 51-60
[20] Ying Wu, Jianhui Jiang, and Liangliang Kong, "Sequential frequency vector based system call anomaly detection," Proceedings of IEEE 16th Pacific Rim International Symposium on Dependable Computing, IEEE Computer Society, Tokyo, Dec 2010, pp. 215-222
[21] Jie Yin and Jianhui Jiang, "An asynchronous checkpoint-based redundant multithreading architecture," Proceedings of IEEE 16th Pacific Rim International Symposium on Dependable Computing, IEEE Computer Society, Tokyo, Dec 2010, pp. 243-244
[22] Jie Yin and Jianhui Jiang, "Design and analysis of an asynchronous checkpoint-based redundant multithreading architecture," Dependable Computing, Vol. 25, TSI Press, 2010, pp. 519-524
[23] Ying Wu and Jianhui Jiang, "Frequency weighted Hamming distance for system call anomaly detection," Proceedings of the WRI World Congress on Computer Science and Information Engineering, Los Angeles, CA, 31 March - 2 April 2009, pp. 105-109
[24] Jianhui Jiang, Hongbao Shi, Yinghua Min, and Xiaodong Zhao, "A novel NMR structure with concurrent output error location capability," Proceedings of 1999 Pacific Rim International Symposium on Dependable Computing, IEEE Computer Society, Hong Kong, Dec 1999, pp. 32-39

 

Software Reliability Engineering
[1] Hu Jiawei, Jiang Jianhui, "Design and implementation of a fault injection mechanism for software reliability evaluation," Journal of Computer-Aided Design & Computer Graphics, Vol. 24, No. 6, pp. 741-751, 2012 (in Chinese)
[2] JIN Ang, JIANG Jian-Hui, LOU Jun-Gang, "Dependability benchmarking based on accelerated life test and its application to Web server test," Journal of Computer Research and Development, Vol. 47, No. S, pp. 229-236, 2011 (in Chinese)
[3] JIN Ang, JIANG Jian-hui, LOU Jun-gang, HU Jia-wei, "A PIN-based dynamic software fault injection system," Journal of Communication and Computer, Vol. 6, No. 1, pp. 24-33, 2009
[4] Liu Hongtao and Jiang Jianhui, "A robustness testing platform for file system," High Technology Letters, Vol. 12, No. S, pp. 23-27, 2006
[5] LOU Jungang, JIANG Jianhui, JIN Ang, "Study on software reliability model considering the warps between different software failure processes," Chinese Journal of Computers, Vol. 33, No. 7, pp. 1279-1287, 2010 (in Chinese)
[6] Zhang Rui, Jiang Jianhui, Lou Jungang, Shen Junhua, Wang Yanna, "A B/S structure based test platform for embedded systems and its applications," Journal of Computer-Aided Design & Computer Graphics, Vol. 21, No. 1, pp. 13-18, 2009 (in Chinese)
[7] LIANG Jian-hua, JIANG Jian-hui, JIN Ang, HU Jin, "Software-implemented transient fault injection for Linux," Journal of Tongji University (Nature Science), Vol. 34, No. 6, pp. 823-827, 2006 (in Chinese)
[8] Jianhui Jiang, Xiaodong Zhao, Mei Tong, and Yingxin Gao, "The combinational transaction block and its implementation in C language and FOXPRO," Journal of Computer Research and Development, Vol. 35, No. 9, pp. 859-864, 1998 (in Chinese)
[9] Jungang Lou, Jianhui Jiang, and Chunyan Shuai, "A study on software reliability prediction based on transduction inference," Proceedings of IEEE 19th Asian Test Symposium, IEEE Computer Society, Shanghai, Dec 2010, pp. 77-80
[10] Ang Jin and Jianhui Jiang, "Fault injection scheme for embedded programs at machine code level and verification," Proceedings of 15th IEEE Pacific Rim International Symposium on Dependable Computing, IEEE Computer Society, Shanghai, Nov 2009, pp. 55-62
[11] Lou Jun-gang, Jiang Jian-hui, Shuai Chun-yan, Zhang Rui, and Jin Ang, "Software reliability prediction model based on relevance vector machine," Proceedings of 2009 IEEE International Conference on Intelligent Computing and Intelligent Systems, Shanghai, Nov 2009, pp. 229-233
[12] Zhang Rui, Jiang Jianhui, Yin Jie, Jin Ang, Lou Jungang, and Wu Ying, "A new method for test suite reduction," Proceedings of the 9th International Conference for Young Computer Scientists, IEEE Computer Society, Zhang Jia Jie, Nov 2008, pp. 1211-1216
[13] Ang Jin, Jianhui Jiang, Jiawei Hu, and Jungang Lou, "A PIN-based dynamic software fault injection system," Proceedings of the 9th International Conference for Young Computer Scientists, IEEE Computer Society, Zhang Jia Jie, Nov 2008, pp. 2160-2167
[14] Qian Feng-an and Jiang Jian-hui, "A novel test case generation method of pair-wise testing," Proceedings of IEEE 16th Asian Test Symposium, IEEE Computer Society Press, Beijing, Oct 2007, pp. 149-154

 

VLSI/SoC Test and Fault Tolerance
[1] OUYANG Cheng-Tian, JIANG Jian-Hui, "Reliability estimation of sequential circuit based on probabilistic transfer matrices," ACTA ELECTRONICA SINICA, Vol. 41, No. 1, pp. 171-177, 2013 (in Chinese)
[2] XIAO Jie, JIANG Jian-hui, "The Estimation of Fault Probability of Elementary Gates Based on the Layout Structure Information," ACTA ELECTRONICA SINICA, Vol. 40, No. 2, pp. 235-240, 2012 (in Chinese)
[3] Wang Zhen, Jiang Jianhui, "A serial method of circuit reliability calculation based on probabilistic transfer matrix," ACTA ELECTRONICA SINICA, Vol. 37, No. 2, pp. 241-247, 2009 (in Chinese)
[4] WANG Zhen, JIANG Jian-hui, "The calculation of fault infection probability in PTM considering factors of layout," Journal of Harbin Institute of Technology, Vol. 41, No. S1, pp. 124-129, 2009 (in Chinese)
[5] WANG Zhen, JIANG Jianhui, and YANG Guang. Implementation and analysis of probabilistic methods for gate-level circuit reliability estimation. Tsinghua Science and Technology, 2007, 12(S1): 32-38
[6] Wei Wang and Jian-Hui Jiang, "Hardware complexity and fault response rate of a class of online-testing and fault-tolerant structures in Xilinx CPLD," Journal of Harbin Institute of Technology, Vol. 38, No. S, pp. 412-416, 2006
[7] Jian-Hui Jiang, "An error recoverable structure based on complementary logic and alternating-retry," Journal of Computer Science and Technology, Vol. 20, No. 6, pp. 885-894, 2005
[8] JIANG Jian-Hui and YUN Chun-Xin, "Online testing techniques for chip-level systems," Journal of Computer Research and Development, Vol. 41, No. 9, pp. 1593-1603, 2004 (in Chinese)
[9] CHEN Huo-jun, JIANG Jian-hui, "Mappings of gate-level faults to register transfer level faults," Journal of Tongji University (Nature Science), Vol. 32, No. 8, pp. 1061-1066, 2004 (in Chinese)
[10] JIANG Jian-Hui, ZHU Wei-Guo, "A survey on built-in self-test and built-in self-repair of embedded memories," Journal of Tongji University (Nature Science), Vol. 32, No. 8, pp. 1050-1056, 2004 (in Chinese)
[11] JIANG Jian-Hui, MIN Ying-Hua, PENG Cheng-Lian, "A robust fail-Safe interface used for dual modular systems," Journal of Tongji University (Nature Science), Vol. 30, No. 10, pp. 1164-1168, 2002 (in Chinese)
[12] JIANG Jian-Hui, MIN Ying-Hua, SHI Hong-Bao, "The concepts and basic structures of concurrent error location for digital circuits," Journal of Computer Research and Development, Vol. 37, No. 5, pp. 532-542, 2000 (in Chinese)
[13] Jianhui Jiang, Yinghua Min, and Hongbao Shi, "New concepts of concurrent error detection of digital circuits," Journal of Computer Research and Development, Vol. 36, No. 9, pp. 1133-1141, 1999 (in Chinese)
[14] Jie Xiao, Jian-Hui Jiang, Xu-Guang Zhu, and Cheng-Tian Ouyang, "A method of circuit reliability estimation based on iterative PTM model," Proceedings of IEEE 17th Pacific Rim International Symposium on Dependable Computing, Pasadena, California, CA, Dec 2011, pp. 276-277
[15] Chengtian Ouyang, Jianhui Jiang and Jie Xiao, "Reliability evaluation of flip-flops based on probabilistic transfer matrices," Proceedings of IEEE 16th Pacific Rim International Symposium on Dependable Computing, IEEE Computer Society, Tokyo, Dec 2010, pp. 239-240
[16] Jian-Hui JIANG, "Error detection and correction in VLSI systems by online testing and retrying," Proceedings of IEEE 12th Asian Test Symposium, IEEE Computer Society Press, Xi'an, Nov 2003, P. 504
[17] Jianhui Jiang and Mou Hu, "The extended self-checking properties of alternating-complementary logic systems," Proceedings of International Workshop on Computer-Aided Design, Test, and Evaluation for Dependability, International Academic Publishers, Beijing, July 1996, pp. 258-263
[18] Jiang Jianhui and Hu Mou, "Fault tolerance and pipelining of VLSI combinational logic networks," Proceedings of IEEE Region 10 International Conference on Computer, Communication, Automation and Power Engineering, vol.1, International Academic Publishers, Beijing, Oct 1993, pp. 44-48
Real-Time Systems
[1] Liangliang Kong and Jianhui Jiang, "A worst-case execution time analysis approach based on independent paths for ARM programs," Wuhan University Journal of Natural Sciences, Vol. 17, No. 5, pp. 391-399, 2012
[2] Kong Liangliang, Jiang Jianhui, Xiao Jie, and Jiang Yuanyuan, "Simulation-based non-linear methods for the estimation of execution cycles of ARM programs," Journal of Computer Research and Development, Vol. 49, No. 2, pp. 392-401, 2012 (in Chinese)
[3] LOU Jungang, JIANG Jianhui, ZHAO Shimin, KONG Liangliang, "Analysis of performance of embedded systems based on randomized complete blocks designs," Journal of Tongji University (Nature Science), Vol. 37, No. 12, pp. 1663-1667, 2009 (in Chinese)
[4] KONG Liang-liang, JIANG Jian-hui, JIN Ang, "Measurement of system performance," Journal of Harbin Institute of Technology, Vol. 41, No. S1, pp. 135-141, 2009 (in Chinese)
[5] JIANG Jianhui and TANG Zhijie, "A novel method to measure real-time performance parameters of embedded operating systems," Journal of Tongji University (Nature Science), Vol. 36, No. 9, pp. 1260-1266, 2008 (in Chinese)
[6] Liangliang Kong, Jianhui Jiang, "A combined hardware/software measurement for ARM program execution time," Communications in Computer and Information Science, Vol. 337, 2013, pp. 185-201
[7] Liangliang Kong and Jianhui Jiang, "A safe measurement-based worst-case execution time estimation using automatic test-data generation," Proceedings of IEEE 16th Pacific Rim International Symposium on Dependable Computing, IEEE Computer Society, Tokyo, Dec 2010, pp. 245-246
[8] Wang Hongcheng, Jiang Jianhui, and Jin Ang, "A performance benchmark suite for real-time embedded systems," High Technology Letters, Vol. 12, No. S, pp. 55-59, 2006

 

Reconfigurable Systems
[1] CHEN Nai-jin, JIANG Jian-hui, "A hardware-task partitioning algorithm merged area estimation with multi-objective optimization," Journal on Communications, Vol. 34, No. 2, pp. 40-55, 2013 (in Chinese)
[2] CHEN Nai-jin, JIANG Jian-hui, CHEN Xin, ZHOU Zhou, XU Ying, "An improved level partitioning algorithm considering minimum execution delay and resource restraints," ACTA ELECTRONICA SINICA, Vol. 40, No. 5, pp. 1055-1066, 2012 (in Chinese)
[3] Naijin Chen and Jianhui Jiang, "Mapping algorithm for coarse-grained reconfigurable multimedia architectures," Proceedings of 19th IEEE Reconfigurable Architectures Workshop, IEEE Computer Society, Shanghai, China, 2012, pp. 281-286

 

Computer-Aided Engineering
[1] Bu Deng-li and Jiang Jian-hui, "Hybrid multi-valued discrete particle swarm optimization algorithm for mixed-polarity Reed-Muller minimization," Journal of Electronics & Information Technology, Vol. 35, No. 2, pp. 361-367, 2013 (in Chinese)
[2] Bu Dengli and Jiang Jianhui, "Area optimization of MPRM circuits based on coefficient matrix transformation," Journal of Computer-Aided Design & Computer Graphics, Vol. 25, No. 1, pp. 126-135, 2013 (in Chinese)

 

Current Projects:
Huawei Technologies Co., Ltd. Project: Research on Fault Modes of Linux and Test Technology based on Fault Injection.
The National High Technology Research and Development Program (863 Program) Project: Research on Software Dependability Assessment Methods, Tools and Applications.
National Science Foundation of China: Research on Low Cost Fault Tolerant Techniques for Hard Errors of Microprocessors.

 

Professional Activities:
Vice Director, Technical Committee on Fault-tolerant Computing, CCF, 2012-present
Member, Technical Committee on Microcomputer, CCF, 2008-present
Editorial Board Member, Journal of Circuits and Systems, China, 2004-2006
Program Co-Chair, 2010, IEEE 11th Workshop on RTL and High Level Testing (WRTLT)
Tutorial Chair, 2010, IEEE 19th Asian Test Symposium (ATS)
Program Committee member, 2009-2011, IEEE Pacific Rim International Symposium on Dependable Computing (PRDC)
Program Committee member, 2007 and 2010 IEEE ATS
Program Committee member, 2003 and 2007 IEEE WRTLT
Program Committee member, 2011 IEEE Workshop on Dependable and Secure Nanocomputing (WDSN)
Program Chair, 2004, Chinese Symposium on Dependable Computing and Applications
Program Co-Vice Chair, 2006 and 2010, Chinese Test Conference
Program Committee member, 2002, 2004, 2008 and 2012, Chinese Test Conference
Program Committee member, 2003, 2005, 2007, 2009, 2011 and 2013, Chinese Conference on Fault Tolerant Computing
Program Committee member, 2007, 2009 and 2011, Chinese Software Test Symposium

 

Awards and Honors:
Outstanding Postdoctor, Fudan University, China, 2006
Excellent Young Scientist and Engineer, Railway Ministry of CHINA, 1998
Baosteel Excellent Teacher Award, Baosteel Education Fund, 1997
Excellent Young Teacher of University, Shanghai Education Commission, Shanghai, China, 1997 and 1995

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